SkyEgg: Heterogeneity-Aware Hardware Synthesis via Equality Saturation

תקציר מקורי באנגליתarXiv:2511.15323v2 Announce Type: replace-cross Abstract: Hardware synthesis is a key interface between high-level programs and accelerator designs. Modern FPGAs increasingly expose heterogeneity in resource functionality and timing configurability. Exploiting these resources requires synthesis to choose among hardware implementations and fine-grained configuration options, and coordinate these choices across multiple stages. However, prior frameworks fail to fully explore these choices due to resource models confined to per-operation mappings and limited fusion patterns. Moreover, they perform transformation, scheduling, and mapping sequentially, selecting an expression form and assigning cycle boundaries before full mapping information is available. This problem precludes chaining and fu